Data processing devices can employ virtual addressing schemes to address memory space. An operating system at the data processing device provides virtual addresses to hardware that translates the virtual addresses to a system physical address which is used to access memory. In order to translate a virtual address to a system physical address, the translation hardware typically employs a set of page tables. The first page table in the set of page tables is addressed using a portion of the virtual address to access address information, such as a base address. The base address information is combined with a second portion of the virtual address to access a second page table. Each page table in the set is accessed in succession based on address information provided by the previous page table and a portion of the virtual address until the final page table is accessed to retrieve the system physical address associated with the virtual address. This traversal of the set of page tables is referred to as a page walk.
The page walk process can be more complex for data processing devices that employ a hypervisor. The hypervisor supervises memory accesses of one or more operating systems executing at the data processor. Accordingly, the hypervisor isolates the system physical addresses from each operating system by translating the addresses provided by each OS page table, referred to as guest physical addresses, to system physical addresses. For example, the hypervisor can require an additional set of page tables to be traversed between each access to the first set of page tables in order to obtain the system physical address information for the subsequent access. While this ensures that the hypervisor controls the address translation, it can also undesirably increase the amount of time used to translate the virtual address, thereby reducing the efficiency of memory accesses at the data processing device. Accordingly, there is a need for an improved address translation device and methods.